陈思浩 吴黎明 彭克锦 许志杰
（广东工业大学机电工程学院，广东 广州 510006）
摘要：针对卷积神经网络模型规模较大，以及嵌入式系统计算资源有限的问题，提出一种基于ZYNQ平台的卷积神经网络加速器设计方案。采用软硬件协同设计的原则，首先，在FPGA端设计图像、参数输入模块；然后，利用FPGA并行计算技术实现卷积层和池化层运算，并通过摄像头采集手写数字图像与LCD显示结果；最后，在嵌入式平台上实现手写数字识别。实验结果表明，卷积层和池化层的运算速度比ARM平台提高了2.68倍。
关键词：卷积神经网络；ZYNQ平台；硬件加速；FPGA
中图分类号：TN912.3 文献标志码：A 文章编号：1674-2605(2024)01-0005-05
DOI：10.3969/j.issn.1674-2605.2024.01.005
Design and Implementation of Convolutional Neural Network Accelerator Based on ZYNQ Platform
CHEN Sihao WU Liming PENG Kejin XU Zhijie
(School of Electromechanical Engineering, Guangdong University of Technology, Guangzhou 510006, China)
Abstract: A convolutional neural network accelerator design scheme based on the ZYNQ platform is proposed to address the issues of large-scale convolutional neural network models and limited computing resources in embedded systems. Adopting the principle of software hardware collaborative design, first, design image and parameter input modules on the FPGA side; Then, using FPGA parallel computing technology to implement convolutional and pooling layer operations, and capturing handwritten digital images and LCD display results through a camera; Finally, implement handwritten digit recognition on an embedded platform. The experimental results show that the computational speed of the convolutional and pooling layers is 2.68 times faster than that of the ARM platform.
Keywords: convolutional neural networks; ZYNQ platform; hardware acceleration; FPGA
